Analog-to-digital converters (ADC) are in widespread use today; in electronics for consumers, industrial applications, etc. Typically, analog-to-digital converters include circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is typically in the form of either a parallel word or a serial digital bit string. There are many types of analog-to-digital conversion schemes such as voltage to frequency conversion, charge redistribution, delta modulation, as well as others. Typically, each of these conversion schemes has its advantages and disadvantages. One type of analog-to-digital converter that has seen increasing use is the switched capacitor sigma-delta converter.
FIG. 1A shows the principle block diagram of a sigma-delta ADC. A loop filter 10 receives the analog input value and is connected to a quantizer 20. The quantizer can generate a single bit output or in other embodiments is operable to generate multiple distinct, output levels that can be encoded in an n-bits bit steam. This single bit output or n bits bit stream is fed back to a DAC 30 which generates an output signal that is fed to the loop filter 10. In a sigma-delta analog-to-digital converter (ADC), the bitstream (1-bit or multi-bit) is then usually processed by a digital decimation filter to produce a decimated higher resolution digital word that represents the input signal.
The stable input range of any high order sigma-delta modulator used in a sigma delta converter is limited to a fraction of the reference voltage. Outside of this stable input range the error becomes very large and the modulator gives erroneous results. Therefore, the signal must be attenuated to stay in this stable input range (S/R<1), where S is the signal voltage and R is the reference voltage. The minimal attenuation depends on the modulator order and on the number of levels in the DAC, it is typically a larger attenuation with a larger modulator order and with a lower number of DAC levels. In order to achieve a final gain of 1, the signal attenuation can be compensated in the digital section. FIG. 1B shows an example of the distribution of quantization noise depending on the normalized differential input value for a 3rd order 1-bit sigma-delta modulator. Here the input signal must be attenuated to ⅔ of the nominal value to ensure low noise. Above this range the modulator becomes unstable.
The input and DAC voltage are sampled on capacitors (or pairs of capacitors for differential voltages) inside the loop filter of the delta-sigma modulator. However, if these voltages are sampled on different capacitors, the mismatch error of the capacitors will produce a gain error on the output result of the sigma-delta ADC. In order to prevent this mismatch, one of the solutions is to sample the signal and the DAC voltages on the same capacitors, this way there is no mismatch error and the gain error is cancelled. However since there is a need of scaling the inputs with a S/R<1 ratio, the capacitors for the signal and the DAC voltages have to be different in size. The other drawback of this technique is that you cannot sample two voltages on one capacitors, so the sampling of the input signal and DAC voltage have to be done one after the other resulting in a 4-phase system: 2 phases to sample and transfer charges coming from the input signals, and then 2 phases to sample and transfer charges coming from DAC voltage. This 4-phase system is less efficient because the sampling is done in series and consumes more time than if the DAC voltage and input voltage sampling were done in parallel.
Today's state of the art in sigma-delta modulators for achieving a low part-per-million (ppm) level gain error and reduce impact of the mismatch of the capacitors used to sample DAC and input signal voltages, the sampling capacitors are divided into R groups of same size capacitors. At each sample, a number of capacitors groups S, with S≦R is used to sample and transfer the input signal voltage during the first two phases. At the same time, R-S groups of capacitors are sampling a common mode voltage signal (or ground for a single-ended circuit), which contribution to the total charge transferred is zero. All R groups of capacitors are used to sample and transfer the DAC voltage during the last two phases. The S/R, ratio is well achieved here by using this technique. In order to minimize the mismatch effects, the S groups of capacitors are chosen among the R groups differently at each sample with a certain sequence so that all the R groups of capacitors have sampled the same amount of times the input signal after a certain period of time. This sequence is rotating the input capacitors (the ones that sample the input voltage) in order to average the mismatch errors and this technique can diminish drastically the gain error down to the low ppm levels if the average is done for a certain amount of samples.
However requiring four steps (phases) per sample limits the sample rate of the sigma-delta modulator, and/or requires much faster operating speed (faster clocking and higher frequency operation components with a subsequence increase in power usage) of the sigma-delta modulator to complete a signal conversion in a desired time frame. Therefore what is needed is a sigma-delta modulator that has faster, sampling rates that could use only two phases, instead of four with less power consumption while maintaining a very low gain error (2 phases is the minimum number one can achieve because there is a need for a sampling and a transfer of the charge at the inputs).